NUAA campus

Cryogenic Chip Design for High-Performance Computing

Cryogenic Ternary Computing Chip

Cryogenic Ternary Computing Chip

About Us

Our research focuses on high-performance hardware design for domain-specific accelerators and next-generation AI computing systems. We explore novel device, circuit, and architecture solutions to improve memory bandwidth, throughput, and energy efficiency in conventional computing platforms. Our research interests include:

Processing-in-Memory Accelerator Design (Based on SRAM, eDRAM, and emerging memory technologies)

VLSI System Design (Including FPGA-based accelerators and System-on-Chip design)

Cryogenic CMOS Circuit Design (For cryogenic memory and computing circuits)

News

Current
We are looking for self-motivated students to work with us on AI accelerators and SoC chips.
06/2026
Our team won the 3rd Prize in the ITC-Asia 2026 competition. Congratulations to Wenkai Mo, Jiacheng Zou, Yi Tang, and all team members!
06/2026
Our work on cryogenic computing (ternary logic-in-memory accelerator) has been accepted by top-tier IEEE Journal of Solid-State Circuits (JSSC)! Congratulations to Bin🎉
05/2026
Invited talk at the SiG Workshop (Cryo-Electronics for Quantum Systems and HPC), ISCAS 2026, titled "Energy-Efficient eDRAM-Based Cryogenic In-Memory Computing Accelerator."
04/2026
Our 12th-15th test-chips have been submitted for fabrication using 28nm technology. Great jobs!
02/2026
A paper entitled, "DSHD-CAM: High-Throughput RRAM CAM Leveraging Dynamic Shifted Hamming Distance for Genome Analysis" has been accepted in IEEE Transactions on Very Large Scale Integration Systems and is now available in IEEE Xplore.
12/2025
A paper entitled, "Design of An Aging-aware Memory with BTI-mitigated SA and System-Visible Lifetime Management" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
11/2025
A paper entitled, "ACIMC: A 342.7-TOPS/mm² eDRAM-based Analog Cryogenic In-Memory Computing Macro" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
09/2025
A paper entitled, "A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
09/2025
Wenkai Mo joined our research group as a Master's student. Welcome!
07/2025
A paper entitled, "A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory" has been accepted in IEEE Transactions on Very Large Scale Integration Systems and is now available in IEEE Xplore.
04/2025
A paper entitled, "HDD-RAM: A 40-nm 0.35V 25MHz Half-Select Disturb-Free Memory with Data-Aware 10T SRAM" has been published in Integrated Circuits and Systems and is now available in IEEE Xplore.

Teaching

  • Graduate Courses:
    • VLSI Circuit and System Design (TBD)
    • Advanced Digital Integrated Circuits Design (2024~2025, Spring)
  • Undergraduate Courses:
    • Digital Integrated Circuits Design (2025~2026, Fall)
    • FPGA Design and Applications (2025~2026, Fall)